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? semiconductor components industries, llc, 2016 may, 2017 ? rev. 0 1 publication order number: kai ? 29052/d kai-29052 6576 (h) x 4384 (v) interline ccd image sensor description the kai ? 29052 image sensor is a 29 megapixel ccd in a 35 mm optical format that provides increased quantum efficiency (particularly for nir wavelengths) compared to members of the standard 5.5 m family. the sensor shares the same broad dynamic range, excellent imaging performance, and flexible readout architecture as other members of the 5.5 m pixel family. however, qe at 820 nm has been approximately doubled compared to existing devices, enabling enhanced sensitivity without a corresponding decrease in the modulation transfer function (mtf) of the device. the sensor is available with the sparse color filter pattern, which provides a 2 improvement in light sensitivity compared to a standard color bayer part. the kai ? 29052 is drop-in compatible with the kai ? 29050 image sensor, simplifying adoption by camera manufacturers currently working with the kai ? 29050. table 1. general specifications parameter typical value architecture interline ccd; progressive scan total number of pixels 6644 (h) 4452 (v) number of effective pixels 6600 (h) 4408 (v) number of active pixels 6576 (h) 4384 (v) pixel size 5.5 m (h) 5.5 m (v) active image size 36.17 mm (h) 24.11 mm (v) 43.47 mm (diag.), 35 mm optical format aspect ratio 3:2 number of outputs 1, 2, or 4 charge capacity 20,000 electrons output sensitivity 35 v/e quantum efficiency pan ( ? axa, ? qxa, ? pxa) r, g, b ( ? fxa, ? qxa) 43%, 12%, 5% (540, 850, 920 nm) 39%, 40%, 37% (620, 540, 480 nm) read noise (f = 40 mhz) 10 electrons rms dark current photodiode vccd 7 electrons/s 140 electrons/s dark current doubling temp. photodiode vccd 7 c 9 c dynamic range 66 db charge transfer efficiency 0.999999 blooming suppression > 300 x smear estimated ?100 db image lag < 10 electrons maximum pixel clock speed 40 mhz maximum frame rates quad output dual output single output 4 fps 2 fps 1 fps package 72 pin pga cover glass ar coated, 2 sides note: all parameters are specified at t = 40 c unless otherwise noted. features ? increased qe, with 2 improvement at 820 nm ? bayer color pattern, sparse color pattern, and monochrome configurations ? progressive scan readout ? flexible readout architecture ? high frame rate ? low noise architecture ? excellent smear performance ? package pin reserved for device identification applications ? industrial imaging and inspection ? medical imaging ? security and surveillance www.onsemi.com figure 1. kai ? 29052 ccd image sensor see detailed ordering and shipping information on page 2 of this data sheet. ordering information
kai ? 29052 www.onsemi.com 2 ordering information table 2. ordering information part number description marking code kai ? 29052 ? axa ? jd ? b1 monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 29052 ? axa serial number kai ? 29052 ? axa ? jd ? b2 monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 29052 ? axa ? jd ? ae monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 29052 ? fxa ? jd ? b1 gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 29052 ? fxa serial number kai ? 29052 ? fxa ? jd ? b2 gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai ? 29052 ? fxa ? jd ? ae gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 29050 ? qxa ? jd ? b1 gen2 color (sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 29052 ? qxa serial number kai ? 29050 ? qxa ? jd ? ae gen2 color (sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade table 3. evaluation support part number description g2 ? fpga ? bd ? 14 ? 40 ? a ? gevk fpga board for it ? ccd evaluation hardware kai ? 72pin ? head ? bd ? a ? gevb 72 pin imager board for it ? ccd evaluation hardware lens ? mount ? kit ? c ? gevk lens mount kit for it ? ccd evaluation hardware see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com .
kai ? 29052 www.onsemi.com 3 device description architecture figure 2. block diagram 22 dark 22 v1b 12 buffer 12 12 22 ???????????????????? ???????????????????? ???????????????????? ???????????????????? ???????????????????? ???????????????????? h1s) v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 822101 12 8 22 10 1 12 8 22 10 1 12 822101 12 22 12 devid 6576 (h) 4384 (v) 5.5 m 5.5 m pixels fdgcd fdgcd fdgab fdgab dark reference pixels there are 22 dark reference rows at the top and 22 dark rows at the bottom of the image sensor. the dark rows are not entirely dark and so should not be used for a dark reference level. use the 22 dark columns on the left or right side of the image sensor as a dark reference. under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. dummy pixels within each horizontal shift register there are 11 leading additional shift phases. these pixels are designated as dummy pixels and should not be used to determine a dark reference level. in addition, there is one dummy row of pixels at the top and bottom of the image. active buffer pixels 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. these pixels are light sensitive but are not tested for defects and non-uniformities. image acquisition an electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at each photo-site. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. when the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. esd protection adherence to the power-up and power-down sequence is critical. failure to follow the proper power-up and power-down sequences may cause damage to the sensor. see power-up and power-down sequence section.
kai ? 29052 www.onsemi.com 4 bayer color filter pattern figure 3. bayer color filter pattern 22 dark 22 v1b 12 buffer 12 12 22 ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? h1s) v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h 2sld ogd h2slb ogb esd esd sub sub 822101 12 8 22 10 1 12 8 22 10 1 12 822101 12 22 12 devid bg g r bg g r bg g r bg g r 6576 (h) 4384 (v) 5.5 m 5.5 m pixels fdgcd fdgab fdgab fdgcd sparse color filter pattern figure 4. sparse color filter pattern 22 dark 22 v1b 12 buffer 12 12 22 ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? h1s) v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h 2sla oga h 2slc ogc h 2sld ogd h 2slb ogb esd esd sub sub 822101 12 8 22 10 1 12 8 22 10 1 12 822101 12 22 12 devid p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p 6576 (h) 4384 (v) 5.5 m 5.5 m pixels fdgcd fdgab fdgab fdgcd
kai ? 29052 www.onsemi.com 5 physical description pin description and device orientation figure 5. package pin description (top view) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 v3b pixel (1,1) v3b v1b v1b vdda vddb gnd ra gnd rb h2sla h2slb h1ba h1bb h2sa h2sb sub n/c v3t v3t v1t v1t vddc vddd gnd rc gnd rd h2slc h2sld h1bc h1bd h2sc h2sd n/c sub v4b esd v4b v2b v2b vouta voutb rda rdb oga ogb h2ba h2bb h1sa h1sb fdgab fdgab v4t devid v4t v2t v2t voutc voutd rdc rdd ogc ogd h2bc h2bd h1sc h1sd fdgcd fdgcd esd
kai ? 29052 www.onsemi.com 6 table 4. pin description pin name description 1 v3b vertical ccd clock, phase 3, bottom 3 v1b vertical ccd clock, phase 1, bottom 4 v4b vertical ccd clock, phase 4, bottom 5 vdda output amplifier supply, quadrant a 6 v2b vertical ccd clock, phase 2, bottom 7 gnd ground 8 vouta video output, quadrant a 9 ra reset gate, quadrant a 10 rda reset drain, quadrant a 11 h2sla horizontal ccd clock, phase 2, storage, last phase, quadrant a 12 oga output gate, quadrant a 13 h1ba horizontal ccd clock, phase 1, barrier, quadrant a 14 h2ba horizontal ccd clock, phase 2, barrier, quadrant a 15 h2sa horizontal ccd clock, phase 2, storage, quadrant a 16 h1sa horizontal ccd clock, phase 1, storage, quadrant a 17 sub substrate 18 fdgab fast line dump gate, bottom 19 n/c no connect 20 fdgab fast line dump gate, bottom 21 h2sb horizontal ccd clock, phase 2, storage, quadrant b 22 h1sb horizontal ccd clock, phase 1, storage, quadrant b 23 h1bb horizontal ccd clock, phase 1, barrier, quadrant b 24 h2bb horizontal ccd clock, phase 2, barrier, quadrant b 25 h2slb horizontal ccd clock, phase 2, storage, last phase, quadrant b 26 ogb output gate, quadrant b 27 rb reset gate, quadrant b 28 rdb reset drain, quadrant b 29 gnd ground 30 voutb video output, quadrant b 31 vddb output amplifier supply, quadrant b 32 v2b vertical ccd clock, phase 2, bottom 33 v1b vertical ccd clock, phase 1, bottom 34 v4b vertical ccd clock, phase 4, bottom 35 v3b vertical ccd clock, phase 3, bottom 36 esd esd protection disable pin name description 72 esd esd protection disable 71 v3t vertical ccd clock, phase 3, top 70 v4t vertical ccd clock, phase 4, top 69 v1t vertical ccd clock, phase 1, top 68 v2t vertical ccd clock, phase 2, top 67 vddc output amplifier supply, quadrant c 66 voutc video output, quadrant c 65 gnd ground 64 rdc reset drain, quadrant c 63 rc reset gate, quadrant c 62 ogc output gate, quadrant c 61 h2slc horizontal ccd clock, phase 2, storage, last phase, quadrant c 60 h2bc horizontal ccd clock, phase 2, barrier, quadrant c 59 h1bc horizontal ccd clock, phase 1, barrier, quadrant c 58 h1sc horizontal ccd clock, phase 1, storage, quadrant c 57 h2sc horizontal ccd clock, phase 2, storage, quadrant c 56 fdgcd fast line dump gate, top 55 n/c no connect 54 fdgcd fast line dump gate, top 53 sub substrate 52 h1sd horizontal ccd clock, phase 1, storage, quadrant d 51 h2sd horizontal ccd clock, phase 2, storage, quadrant d 50 h2bd horizontal ccd clock, phase 2, barrier, quadrant d 49 h1bd horizontal ccd clock, phase 1, barrier, quadrant d 48 ogd output gate, quadrant b 47 h2sld horizontal ccd clock, phase 2, storage, last phase, quadrant d 46 rdd reset drain, quadrant d 45 rd reset gate, quadrant d 44 voutd video output, quadrant d 43 gnd ground 42 v2t vertical ccd clock, phase 2, top 41 vddd output amplifier supply, quadrant d 40 v4t vertical ccd clock, phase 4, top 39 v1t vertical ccd clock, phase 1, top 38 devid device identification 37 v3t vertical ccd clock, phase 3, top 1. like named pins are internally connected and should have a common drive signal. 2. n/c pins (19, 55) should be left floating.
kai ? 29052 www.onsemi.com 7 imaging performance table 5. typical operation conditions (unless otherwise noted, the imaging performance specifications are measured using the following conditions.) description condition light source (note 1) continuous red, green and blue led illumination operation nominal operating voltages and timing 1. for monochrome sensor, only green led used. table 6. specifications description symbol min. nom. max. unit sampling plan temperature tested at ( c) all configurations dark field global non-uniformity dsnu ? ? 5 mvpp die 27, 40 bright field global non-uniformity (note 1) ? 2 5 %rms die 27, 40 bright field global peak to peak non-uniformity (note 1) prnu ? 10 30 %pp die 27, 40 maximum photo-response non-linearity (note 2) nl ? 2 ? % design maximum gain difference between outputs (note 2) g ? 10 ? % design maximum signal error due to non-linearity differences (note 2) nl ? 1 ? % design horizontal ccd charge capacity h ne ? 50 ? ke ? design vertical ccd charge capacity v ne ? 40 ? ke ? design photodiode charge capacity (note 3) p ne ? 20 ? ke ? die 27, 40 horizontal ccd charge transfer efficiency hcte 0.999995 0.999999 ? die vertical ccd charge transfer efficiency vcte 0.999995 0.999999 ? die photodiode dark current i pd ? 7 70 e/p/s die 40 vertical ccd dark current i vd ? 140 400 e/p/s die 40 image lag lag ? ? 10 e ? design anti-blooming factor x ab 300 ? ? design vertical smear smr ? ? 100 ? db design read noise (note 4) n e ? t ? 10 ? e ? rms design dynamic range (notes 4, 5) dr ? 66 ? db design output amplifier dc offset v odc ? 9.4 ? v die 27, 40 output amplifier bandwidth (note 6) f ? 3db ? 250 ? mhz die output amplifier impedance r out ? 127 ? die 27, 40 output amplifier sensitivity v/ n ? 35 ? v/e ? design
kai ? 29052 www.onsemi.com 8 table 6. specifications description symbol min. nom. max. unit sampling plan temperature tested at ( c) kai ? 29052 ? axa and kai ? 29052 ? qxa configurations peak quantum efficiency qe max ? 43 ? % design peak quantum efficiency wavelength qe ? 540 ? nm design quantum efficiency (850 nm) qe max ? 12 ? nm design peak quantum efficiency (920 nm) qe max ? 5 ? nm design kai ? 29052 ? fba and kai ? 29052 ? qba gen2 color configurations peak quantum efficiency blue green red qe max ? ? ? 37 40 39 ? ? ? % design peak quantum efficiency wavelength blue green red qe ? ? ? 480 540 620 ? ? ? nm design 1. per color 2. value is over the range of 10% to 90% of photodiode saturation. 3. the operating value of the substrate voltage, v ab , will be marked on the shipping container for each device. the value of v ab is set such that the photodiode charge capacity is 700 mv. 4. at 40 mhz. 5. uses 20 log (p ne / n e ? t ). 6. assumes 5 pf load.
kai ? 29052 www.onsemi.com 9 typical performance curves quantum efficiency monochrome with microlens figure 6. monochrome with microlens quantum efficiency 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 absolute quantum efficiency wavelength (nm) kai ? 29052 kai ? 29050 measured with ar coated cover glass
kai ? 29052 www.onsemi.com 10 color (bayer rgb) with microlens figure 7. color (bayer rgb) with microlens quantum efficiency 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 absolute quantum efficiency wavelength (nm) kai ? 29052 red kai ? 29052 green kai ? 29052 blue kai ? 29050 red kai ? 29050 green kai ? 29050 blue measured with ar coated cover glass color (sparse fca) with microlens figure 8. color (sparse cfa) with microlens quantum efficiency 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 absolute quantum efficiency wavelength (nm) pan red green blue measured with ar coated cover glass
kai ? 29052 www.onsemi.com 11 angular quantum efficiency for the curves marked ?horizontal?, the incident light angle is varied in a plane parallel to the hccd. for the curves marked ?vertical?, the incident light angle is varied in a plane parallel to the vccd. monochrome with microlens figure 9. monochrome with microlens angular quantum efficiency ? 40 angle (degrees) relative quantum efficiency (%) 100 vertical horizontal ? 30 ? 20 ? 10 0 10 20 30 40 90 80 70 60 50 40 30 20 10 0 dark current vs. temperature figure 10. dark current vs. temperature 2.9 dark current (e/s/pixel) 100 photodiode vccd 10 1 0.1 1000 10000 72 3 60 3.1 50 3.2 40 3.3 30 3.4 21 1000/t (k) t ( c)
kai ? 29052 www.onsemi.com 12 power ? estimated figure 11. power 0.0 0.5 1.0 1.5 2.0 2.5 10 15 20 25 30 35 40 hccd frequency (mhz) power (w) single dual quad frame rates figure 12. frame rates 0 10 15 20 25 30 35 40 hccd frequency (mhz) frame rate (fps) 0 0.5 0.5 1.0 1.0 1.5 1.5 2.0 2.0 2.5 2.5 3.0 3.0 3.5 3.5 4.0 4.0 4.5 4.5 5.0 5.0 single dual (left/right) quad
kai ? 29052 www.onsemi.com 13 defect definitions table 7. operation conditions for defect testing at 40 c description condition operational mode two outputs, using vouta and voutc, continuous readout hccd clock frequency 10 mhz pixels per line (note 1) 6800 lines per frame (note 2) 2320 line time 715.7 s frame time 1660.5 ms photodiode integration time (pd_tint) mode a: pd_tint = frame time = 1660.5 ms, no electronic shutter used vccd integration time (note 3) 1593.1 ms temperature 40 c light source (note 4) continuous red, green and blue led illumination operation nominal operating voltages and timing 1. horizontal overclocking used. 2. vertical overclocking used. 3. vccd integration time = 2226 lines line time, which is the total time a pixel will spend in the vccd registers. 4. for monochrome sensor, only the green led is used. table 8. defect definitions for testing at 40 c description definition grade 1 grade 2 mono grade 2 color major dark field defective bright pixel (note 1) pd_tint = mode a defect 565 mv 270 540 540 major bright field defective dark pixel (note 1) defect 12% minor dark field defective bright pixel pd_tint = mode a defect 282 mv 2700 5400 5400 cluster defect (note 2) a group of 2 to 19 contiguous major defective pixels, but no more than 4 adjacent defects horizontally 20 n/a n/a cluster defect (note 2) a group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally n/a 50 50 column defect (note 2) a group of more than 10 contiguous major defective pixels along a single column 0 7 27 1. for the color devices (kai ? 29052 ? cxa and kai ? 29052 ? qxa), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ).
kai ? 29052 www.onsemi.com 14 table 9. operation conditions for defect testing at 27 c description condition operational mode two outputs, using vouta and voutc, continuous readout hccd clock frequency 10 mhz pixels per line (note 1) 6800 lines per frame (note 2) 2320 line time 715.7 s frame time 1660.5 ms photodiode integration time (pd_tint) mode a: pd_tint = frame time = 1660.5 ms, no electronic shutter used vccd integration time (note 3) 1593.1 ms temperature 27 c light source (note 4) continuous red, green and blue led illumination operation nominal operating voltages and timing 1. horizontal overclocking used. 2. vertical overclocking used. 3. vccd integration time = 2226 lines line time, which is the total time a pixel will spend in the vccd registers. 4. for monochrome sensor, only the green led is used. table 10. defect definitions for testing at 27 c description definition grade 1 grade 2 mono grade 2 color major dark field defective bright pixel (note 1) pd_tint = mode a defect 565 mv 270 540 540 major bright field defective dark pixel (note 1) defect 12% cluster defect (note 2) a group of 2 to 19 contiguous major defective pixels, but no more than 4 adjacent defects horizontally 20 n/a n/a cluster defect (note 2) a group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally n/a 50 50 column defect (note 2) a group of more than 10 contiguous major defective pixels along a single column 0 7 27 1. for the color devices (kai ? 29052 ? cxa and kai ? 29052 ? qxa), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ). defect map the defect map supplied with each sensor is based upon testing at an ambient (27 c) temperature. minor point defects are not included in the defect map. all defective pixels are reference to pixel 1, 1 in the defect maps. see figure 13: regions of interest for the location of pixel 1, 1.
kai ? 29052 www.onsemi.com 15 test definitions test regions of interest image area roi: pixel (1, 1) to pixel (6600, 4408) active area roi: pixel (13, 13) to pixel (6588, 4396) center roi: pixel (3251, 2155) to pixel (3350, 2254) only the active area roi pixels are used for performance and defect tests. overclocking the test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. see figure 13 for a pictorial representation of the regions of interest. figure 13. regions of interest vouta 1, 1 13, 13 pixel pixel v o utc 22 dark columns 12 buffer columns horizontal overclock 22 dark columns 12 buffer columns 22 dark rows 12 buffer rows 12 buffer rows 22 dark rows 6576 x 4384 active pixels
kai ? 29052 www.onsemi.com 16 tests dark field global non-uniformity this test is performed under dark field conditions. the sensor is partitioned into 1536 sub regions of interest, each of which is 137 by 137 pixels in size. the average signal level of each of the 1536 sub regions of interest is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: (eq. 1) signal of roi[i] (roi average in counts horizontal overclock average in counts) mv per count [mv] where i = 1 to 1536. during this calculation on the 1536 sub regions of interest, the maximum and minimum signal levels are found. the dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. (eq. 2) dark field global non ? uniformity = maximum signal ? minimum signal [mvpp] global non-uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 490 v). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 700 mv. global non-uniformity is defined as: (eq. 3) global non ? uniformity 100 active area standard deviation active area signal [%rms] global peak to peak non-uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 490 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 700 mv. the sensor is partitioned into 1536 sub regions of interest, each of which is 137 by 137 pixels in size. the average signal level of each of the 1536 sub regions of interest (roi) is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: (eq. 4) signal of roi[i] (roi average in counts horizontal overclock average in counts) mv per count [mv] where i = 1 to 1536. during this calculation on the 1536 sub regions of interest, the maximum and minimum signal levels are found. the global peak to peak uniformity is then calculated as: (eq. 5) global peak to peak non ? uniformity 100 maximum signal minimum signal active area signal [%pp] dark field defect test this test is performed under dark field conditions. the sensor is partitioned into 1536 sub regions of interest, each of which is 137 by 137 pixels in size. in each region of interest, the median value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the ?defect definitions? section. bright field defect test this test is performed with the imager illuminated to a level such that the output is at approximately 490 mv. prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 700 mv. the average signal level of all active pixels is found. the dark threshold is set as: (eq. 6) dark defect threshold = active area signal threshold the sensor is then partitioned into 1536 sub regions of interest, each of which is 137 by 137 pixels in size. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. example for major bright field defective pixels: ? average value of all active pixels is found to be 490 mv ? dark defect threshold: 490 mv ? 12% = 59 mv ? region of interest #1 selected. this region of interest is pixels 13, 13 to pixels 149, 149. ? median of this region of interest is found to be 495 mv. ? any pixel in this region of interest that is (495 ? 59 mv) 436 mv in intensity will be marked defective. ? all remaining 1536 sub regions of interest are analyzed for defective pixels in the same manner.
kai ? 29052 www.onsemi.com 17 operation table 11. absolute maximum ratings description symbol minimum maximum unit operating temperature (note 1) t op ? 50 70 c humidity (note 2) rh 5 90 % output bias current (note 3) i out ? 60 ma off-chip load c l ? 10 pf stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. noise performance will degrade at higher temperatures. 2. t = 25 c. excessive humidity will degrade mttf. 3. total for all outputs. maximum current is ? 15 ma for each output. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivi ty). table 12. absolute maximum voltage ratings between pins and ground description minimum maximum unit vdd , vout (note 1) ? 0.4 17.5 v rd (note 1) ? 0.4 15.5 v v1b, v1t esd ? 0.4 esd + 24.0 v v2b, v2t, v3b, v3t, v4b, v4t esd ? 0.4 esd + 14.0 v fdgab, fdgcd esd ? 0.4 esd + 15.0 v h1s , h1b , h2s , h2b , h2sl , r og (note 1) esd ? 0.4 esd + 14.0 v esd ? 10.0 0.0 v sub (note 2) ? 0.4 40.0 v 1. denotes a, b, c or d. 2. refer to application note using interline ccd image sensors in high intensity visible lighting conditions ? and9183/d .
kai ? 29052 www.onsemi.com 18 power-up and power-down sequence adherence to the power-up and power-down sequence is critical. failure to follow the proper power-up and power-down sequences may cause damage to the sensor. figure 14. power-up and power-down sequence vdd sub esd vccd and fdg hccd low time v+ v ? do not pulse the electronic shutter until esd is stable activate all other biases when esd is stable and sub is above 3 v low warnings regarding power-up and power-down 1. activate all other biases when esd is stable and sub is above 3 v. 2. do not pulse the electronic shutter until esd is stable. 3. vdd cannot be +15 v when sub is 0 v. 4. the vccd clock waveform must not have a negative overshoot more than 0.4 v below the esd voltage. 5. the image sensor can be protected from an accidental improper esd voltage by current limiting the sub current to less than 10 ma. sub and vdd must always be greater than gnd. esd must always be less than gnd. placing diodes between sub, vdd, esd and ground will protect the sensor from accidental overshoots of sub, vdd, and esd during power-up and power-down. see figures shown below. figure 15. vccd overshoots all vccd and fdg clocks absolute maximum overshoot of 0.4 v 0.0 v esd esd ? 0.4 v figure 16. external diode protection esd gnd vdd sub
kai ? 29052 www.onsemi.com 19 dc bias operating conditions table 13. dc bias operating conditions description pins symbol min. nom. max. unit max. dc current reset drain (note 1) rd rd 11.8 12.0 12.2 v 10 a output gate (note 1) og og ? 2.2 ? 2.0 ? 1.8 v 10 a output amplifier supply (notes 1, 2) vdd v dd 14.5 15.0 15.5 v 11.0 ma ground gnd gnd 0.0 0.0 0.0 v ? 1.0 ma substrate (notes 3, 8) sub v sub 5.0 v ab v dd v 50 a esd protection disable (notes 6, 7) esd esd ? 9.2 ? 9.0 ? 8.8 v 50 a output bias current (notes 1, 4, 5) vout i out ? 3.0 ? 7.0 ? 10.0 ma ? 1. denotes a, b, c or d. 2. the maximum dc current is for one output. i dd = i out + i ss . see figure 17. 3. the operating value of the substrate voltage, v ab , will be marked on the shipping container for each device. the value of v ab is set such that the photodiode charge capacity is the nominal p ne (see specifications ). 4. an output load sink must be applied to each vout pin to activate each output amplifier. 5. nominal value required for 40 mhz operation per output. may be reduced for slower data rates and lower noise. 6. adherence to the power-up and power-down sequence is critical. see power-up and power-down sequence section. 7. esd maximum value must be less than or equal to v1_l + 0.4 v and v2_l + 0.4 v. 8. refer to application note using interline ccd image sensors in high intensity visible lighting conditions ? and9183/d . figure 17. output amplifier source follower #1 source follower #2 source follower #3 floating diffusion i ss i dd i out vout vdd r rd hccd og
kai ? 29052 www.onsemi.com 20 ac operating conditions table 14. clock levels description pins (note 1) symbol level min. nom. max. unit capacitance (note 2) vertical ccd clock, phase 1 v1b, v1t v1_l low ? 9.2 ? 9.0 ? 8.8 v 180 nf (note 6) v1_m mid ? 0.2 0.0 0.2 v1_h high 12.8 13.0 14.0 vertical ccd clock, phase 2 v2b, v2t v2_l low ? 9.2 ? 9.0 ? 8.8 v 180 nf (note 6) v2_h high ? 0.2 0.0 0.2 vertical ccd clock, phase 3 v3b, v3t v3_l low ? 9.2 ? 9.0 ? 8.8 v 180 nf (note 6) v3_h high ? 0.2 0.0 0.2 vertical ccd clock, phase 4 v4b, v4t v4_l low ? 9.2 ? 9.0 ? 8.8 v 180 nf (note 6) v4_h high ? 0.2 0.0 0.2 horizontal ccd clock, phase 1 storage h1s h1s_l low ? 5.0 (note 7) ? 4.4 ? 4.2 v 600 pf (note 6) h1s_a amplitude 4.2 4.4 5.0 (note 7) horizontal ccd clock, phase 1 barrier h1b h1b_l low ? 5.0 (note 7) ? 4.4 ? 4.2 v 400 pf (note 6) h1b_a amplitude 4.2 4.4 5.0 (note 7) horizontal ccd clock, phase 2 storage h2s h2s_l low ? 5.0 (note 7) ? 4.4 ? 4.2 v 580 pf (note 6) h2s_a amplitude 4.2 4.4 5.0 (note 7) horizontal ccd clock, phase 2 barrier h2b h2b_l low ? 5.0 (note 7) ? 4.4 ? 4.2 v 400 pf (note 6) h2b_a amplitude 4.2 4.4 5.0 (note 7) horizontal ccd clock, last phase (note 3) h2sl h2sl_l low ? 5.2 ? 5.0 ? 4.8 v 20 pf (note 6) h2sl_a amplitude 4.8 5.0 5.2 reset gate r r_l (note 4) low ? 3.5 ? 2.0 ? 1.5 v 16 pf (note 6) r_h high 2.5 3.0 4.0 electronic shutter (notes 5, 8) sub ves high 29.0 30.0 40.0 v 12 pf (note 6) fast line dump gate fdg fdg_l low ? 9.2 ? 9.0 ? 8.8 v 50 pf (note 6) fdg_h high 4.5 5.0 5.5 1. denotes a, b, c or d. 2. capacitance is total for all like named pins. 3. use separate clock driver for improved speed performance. 4. reset low should be set to ?3 volts for signal levels greater than 40,000 electrons. 5. refer to application note using interline ccd image sensors in high intensity visible lighting conditions ? and9183/d . 6. capacitance values are estimated. 7. if the minimum horizontal clock low level is used (?5.0 v), then the maximum horizontal clock amplitude should be used (5 v amp litude) to create a ?5.0 v to 0.0 v clock. 8. figure 18 shown below shows the dc bias (vsub) and ac clock (ves) applied to the sub pin. both the dc bias and ac clock are referenced to ground. figure 18. substrate and electron shutter reference to ground vsub ves gnd gnd
kai ? 29052 www.onsemi.com 21 device identification the device identification pin (devid) may be used to determine which on semiconductor 5.5 micron pixel interline ccd sensor is being used. table 15. device identification description pins symbol min. nom. max. unit max. dc current device identification (notes 1, 2) devid devid 200,000 300,000 400,000 50 a 1. if the device identification is not used, it may be left disconnected. 2. after device identification resistance has been read during camera initialization, it is recommended that the circuit be disa bled to prevent localized heating of the sensor due to current flow through the r_deviceid resistor. recommended circuit note that v1 must be a different value than v2. figure 19. device identification recommended circuit adc r_external v1 v2 devid gnd kai ? 29052 r_deviceid
kai ? 29052 www.onsemi.com 22 timing table 16. requirements and characteristics description symbol min. nom. max. unit notes photodiode transfer t pd 6 ? ? s vccd leading pedestal t 3p 16 ? ? s vccd trailing pedestal t 3d 16 ? ? s vccd transfer delay t d 4 ? ? s vccd transfer t v 8 ? ? s vccd clock cross-over v vcr 75 ? 100 % 1 vccd rise, fall times t vr , t vf 5 ? 10 % 1, 2 fdg delay t fdg 2 ? ? s hccd delay t hs 1 ? ? s hccd transfer t e 25.0 29.4 ? ns shutter transfer t sub 1 ? ? s shutter delay t hd 1 ? ? s reset pulse t r 2.5 ? ? ns reset ? video delay t rv ? 2.2 ? ns h2sl ? video delay t hv ? 3.1 ? ns line time t line 96.3 110.0 ? s dual hccd readout 179.4 208.7 ? single hccd readout frame time t frame 213.5 246.1 ? ms quad hccd readout 427.0 492.2 ? dual hccd readout 795.1 925.2 ? single hccd readout 1. refer to figure 24: vccd clock rise time, fall time, and edge alignment. 2. relative to the pulse width.
kai ? 29052 www.onsemi.com 23 timing diagrams the timing sequence for the clocked device pins may be represented as one of seven patterns (p1 ? p7) as shown in the table below. the patterns are defined in figure 20 and figure 21. contact on semiconductor application engineering for other readout modes. table 17. timing diagrams device pin quad readout dual readout vouta, voutb dual readout vouta, voutc single readout vouta v1t p1t p1b p1t p1b v2t p2t p4b p2t p4b v3t p3t p3b p3t p3b v4t p4t p2b p4t p2b v1b p1b v2b p2b v3b p3b v4b p4b h1sa p5 h1ba h2sa (note 2) p6 h2ba ra p7 h1sb p5 p5 h1bb p6 h2sb (note 2) p6 p6 h2bb p5 rb p7 p7 (note 1) or off (note 3) p7 (note 1) or off (note 3) h1sc p5 p5 (note 1) or off (note 3) p5 p5 (note 1) or off (note 3) h1bc h2sc (note 2) p6 p6 (note 1) or off (note 3) p6 p6 (note 1) or off (note 3) h2bc rc p7 p7 (note 1) or off (note 3) p7 p7 (note 1) or off (note 3) h1sd p5 p5 (note 1) or off (note 3) p5 p5 (note 1) or off (note 3) h1bd p6 h2sd (note 2) p6 p6 (note 1) or off (note 3) p6 p6 (note 1) or off (note 3) h2bd p5 rd p7 p7 (note 1) or off (note 3) p7 (note 1) or off (note 3) p7 (note 1) or off (note 3) #lines/frame (minimum) 2226 4452 2226 4452 #pixels/line (minimum) 3333 6666 1. for optimal performance of the sensor. may be clocked at a lower frequency. if clocked at a lower frequency, the frequency se lected should be a multiple of the frequency used on the a and b register. 2. h2slx follows the same pattern as h2sx. for optimal speed performance, use a separate clock driver. 3. off = +5 v. note that there may be operating conditions (high temperature and/or very bright light sources) that will cause bl ooming from the unused c/d register into the image area.
kai ? 29052 www.onsemi.com 24 photodiode transfer timing a row of charge is transferred to the hccd on the falling edge of v1 as indicated in the p1 pattern below. using this timing sequence, the leading dummy row or line is combined with the first dark row in the hccd. the ?last line? is dependent on readout mode ? either 2226 or 4452 minimum counts required. it is important to note that, in general, the rising edge of a vertical clock (patterns p1 ? p4) should be coincident or slightly leading a falling edge at the same time interval. this is particularly true at the point where p1 returns from the high (3 rd level) state to the mid-state when p4 transitions from the low state to the high state. figure 20. photodiode transfer timing last line l1 + dummy line p1b p2b p3b p4b pattern l2 p1t p2t p3t p4t p5 p6 p7 1 2 3 4 5 6 t v /2 t v t hs t d t 3p t pd t 3d t v t v /2 t v /2 t hs t v t v /2 t v /2 t v /2 t v t d line and pixel timing each row of charge is transferred to the output, as illustrated below , on the falling edge of h2sl (indicated as p6 pattern). the number of pixels in a row is dependent on readout mode ? either 3333 or 6666 minimum counts required. figure 21. line and pixel timing p1t p5 p6 p7 pixel n pixel 1 pixel 34 vout pattern p1b t e /2 t v t hs t e t r t line t v
kai ? 29052 www.onsemi.com 25 pixel timing detail figure 22. pixel timing detail p5 p6 p7 vout t hv t rv frame/electronic shutter timing the sub pin may be optionally clocked to provide electronic shuttering capability as shown below. the resulting photodiode integration time is defined from the falling edge of sub to the falling edge of v1 (p1 pattern). figure 23. electronic shutter timing p1t/b p6 sub pattern t hd t hd t sub t int t frame vccd clock edge alignment figure 24. vccd clock rise time, fall time, and edge alignment v vcr 90% 10% t vf t vr t v t v t vf t vr
kai ? 29052 www.onsemi.com 26 line and pixel t iming ? vertical binning by 2 p1t p2t p3t p4t p1b p2b p3b p4b p5 p6 p7 vout pixel n pixel 34 pixel 1 t v t hs t v t v t hs figure 25. line and pixel timing ? vertical binning by 2 fast line dump timing the fdg pins may be optionally clocked to efficiently remove unwanted lines in the image resulting for increased frame rates at the expense of resolution. below is an example of a 2 line dump sequence followed by a normal readout line. figure 26. fast line dump timing t fdg t fdg clock v1b v2b fdgab h1s v1t v2t fdgcd h1s
kai ? 29052 www.onsemi.com 27 storage and handling table 18. storage conditions description symbol minimum maximum unit storage temperature (note 1) t st ? 55 80 c humidity (note 2) rh 5 90 % 1. long-term exposure toward the maximum temperature will accelerate color filter degradation. 2. t = 25 c. excessive humidity will degrade mttf. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on environmental exposure, please download the using interline ccd image sensors in high intensity lighting conditions application note (and9183/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kai ? 29052 www.onsemi.com 28 mechanical information completed assembly figure 27. completed assembly (1 of 2) notes: 1. see ordering information for marking code. 2. cover glass not to overhang package holes or outer ceramic edges. 3. glass epoxy not to extend over image array. 4. no materials to interfere with clearance through package holes. 5. units: in [mm].
kai ? 29052 www.onsemi.com 29 figure 28. completed assembly (2 of 2) notes: 1. units: in [mm].
kai ? 29052 www.onsemi.com 30 cover glass figure 29. cover glass notes: 1. substrate = schott d263t eco 2. dust, scratch, inclusion specification: a. 20_m max size in zone a b. zone a = 1.474 1.000 [16.43 10.08] centered 3. mar coated both sides 4. spectral transmission a. 350 ? 365 nm: t 88% b. 365 ? 405 nm: t 94% c. 405 ? 450 nm: t 98% d. 450 ? 650 nm: t 99% e. 650 ? 690 nm: t 98% f. 690 ? 770 nm: t 94% g. 770 ? 870 nm: t 88% 5. units: in [mm]
kai ? 29052 www.onsemi.com 31 cover glass transmission figure 30. cover glass transmission 0 10 20 30 40 50 60 70 80 90 100 200 300 400 500 600 700 800 900 wavelength (nm) transmission (%) on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 kai ? 29052/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

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